Integrated circuitry contained in computers, phones, pagers, and other electronic devices all require high frequency periodic clock signals in order to function. In specific applications, such as portable telephones, the high frequency clock signals must be in phase with a reference clock signal but at a much higher frequency. While frequency reference signals are provided in these applications, the high frequency clock signal must be constructed by the integrated circuitry. Therefore, circuitry has been developed to create high frequency clock signals in phase with, and at multiple frequencies of frequency references. Because frequency reference often have non-unity duty cycles, the high frequency clock signals typically are in phase with a rising edge of the frequency references but may not be in phase with reference to the falling edges of the frequency reference.
FIG. 1 illustrates a circuit commonly used to generate a high frequency clock signal called a phase-locked-loop ("PLL"). The major components of the PLL are a phase detector, a loop filter, a voltage controlled oscillator, and a divide by N element. As is shown, a frequency reference serves as an input to the PLL. The PLL output, in a steady state condition, oscillates at a frequency N times the frequency of the frequency reference and in phase with the rising edges of the frequency reference.
The divide by N circuit element divides the PLL output by N to provide a feedback signal that is compared with the frequency reference at the phase detector. The phase detector, in turn, provides two output signals to a loop filter based upon the relationship between the frequency reference and the feedback signal. A first output signal is called the up-pump. A second output signal is called the down-pump. The up-pump goes active high on a rising edge of the frequency reference while the down-pump signal goes active high on a rising edge of the feedback signal. If, however, one of the output signals is active high and the other output signal goes active high, both of the output signals go low.
Both the up-pump and down-pump are provided as inputs to the loop filter. The loop filter serves to filter out the high frequency components of the signals and to provide an output voltage that serves as an input to, and controls, the voltage controlled oscillator. The voltage controlled oscillator produces a periodic and symmetrical clock signal at a frequency dependent upon the voltage across its inputs.
During steady-state operation, an output of the PLL is at a desired frequency multiple (N times) of the frequency reference and in phase with the frequency reference such that one of the rising edges of the output coincides with each rising edge of the frequency reference. In steady-state, however, because the up-pump rises on a rising edge of the frequency reference and the down-pump signal rises on a rising edge of the feedback signal, one of the output signals rises a short period of time before the other output signal rises. Thus, even in steady-state, each of the output signals goes active high over a short period and then immediately falls. The loop filter serves to filter these transient, high frequency signals so that they do not vary the voltage controlling the voltage controlled oscillator. Therefore, the voltage across the voltage controlled oscillator inputs remains constant in steady-state operation, and resultantly, so does the PLL output.
When the frequency reference and the feedback signal are at different frequencies or the rising edges are not in phase, either the up-pump or down-pump signal remains active high for a longer period. Thus, the loop filter adjusts the voltage across the voltage controlled oscillator and the frequency of the output at the voltage controlled oscillator changes. The adjustments continue until such time as the frequency reference and the feedback signal are in phase and at the same frequency.
During power up, the PLL output rises in frequency until it reaches a steady-state. Over this time period, the PLL output is not available to drive connected circuitry. Without an indication of such, circuitry connected to the PLL may function based on the PLL output and produce erroneous results. Thus, it is desirable to known when the PLL reaches a frequency lock condition and also a phase lock condition. Further, it is desirable to know when the PLL moves away from its steady-state condition. Thus, frequency lock indicators have been devised to signal a frequency lock condition.
As is shown in a lower portion of FIG. 1, a particular prior art frequency lock indicator provide both the up-pump signal and down-pump signal as inputs to an OR gate. The output of the OR gate then serves to charge up a capacitor through a resistor. When the output of the OR gate provides a logic high signal to the capacitor over a sufficient period of time, the OR gate output charges the capacitor above a reference level. When the capacitor voltages reaches this reference level, a counter is reset. If the counter is reset before reaching some predetermined count value, the lock indicator is not set. If, however, the counter reaches the predetermined count value before the it is reset, the lock indicator is set.
The circuit shown in FIG. 1 worked well for high frequencies. At lower frequencies, however, such as those common in telecommunications applications, where 8 KHz is typical, the circuit was not operational. With an 8 KHz frequency reference signal, the amount of capacitance required in the circuit could not readily be provided on an integrated circuit. In addition, such circuits are dependent on the operating frequency.
Thus, a need exists for frequency lock and phase lock indicator circuitry that operates independent of the operating frequency, and for lower frequencies applications, operations without the need for a large capacitor.